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| Not recommended for new designs - Please use 24LCS21A. 24LC21 1K 2.5V Dual Mode I2CTM Serial EEPROM Features: * Single supply with operation down to 2.5V * Completely implements DDC1TM/DDC2TM interface for monitor identification * Low-power CMOS technology: - 1 mA active current typical - 10 A standby current typical at 5.5V * 2-wire serial interface bus, I2CTM compatible * Self-timed write cycle (including auto-erase) * Page-write buffer for up to 8 bytes * 100 kHz (2.5V) and 400 kHz (5V) compatibility * Factory programming (QTP) available * 1,000,000 erase/write cycles ensured * Data retention > 200 years * 8-pin PDIP and SOIC package * Available for extended temperature ranges Commercial (C): 0C to +70C Industrial (I): -40C to +85C Package Types PDIP NC NC NC VSS 1 2 3 4 24LC21 8 7 6 5 VCC VCLK SCL SDA SOIC 1 2 3 4 24LC21 8 7 5 5 NC NC NC VSS VCC VCLK SCL SDA Description: The Microchip Technology Inc. 24LC21 is a 128 x 8 bit Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: Transmit-only mode and Bidirectional mode. Upon power-up, the device will be in the Transmit-only mode, sending a serial bit stream of the entire memory array contents, clocked by the VCLK pin. A valid high-to-low transition on the SCL pin will cause the device to enter the Bidirectional mode, with byte selectable read/write capability of the memory array. The 24LC21 is available in a standard 8-pin PDIP and SOIC package, in both commercial and industrial temperature ranges. Block Diagram VCLK HV Generator I/O Control Logic Memory Control Logic XDEC EEPROM Array Page Latches SDA SCL YDEC VCC VSS Sense Amp R/W Control I2C is a trademark of Philips Corporation. DDC is a trademark of the Video Electronics Standards Association. 2004 Microchip Technology Inc. DS21095J-page 1 24LC21 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() VCC.............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied ................................................................................................-40C to +125C Soldering temperature of leads (10 seconds) .......................................................................................................+300C ESD protection on all pins ...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS VCC = +2.5V to 5.5V Commercial (C): TA = 0C to +70C Industrial (I): TA = -40C to +85C Symbol VIH VIL Min .7 VCC -- Max -- .3 VCC Units V V -- -- VCC 2.7V (Note 1) VCC < 2.7V (Note 1) (Note 1) IOL = 3 mA, VCC = 2.5V (Note 1) IOL = 6 mA, VCC = 2.5V VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note1), TA = 25C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC (Note 2) Conditions DC CHARACTERISTICS Parameter SCL and SDA pins: High-level input voltage Low-level input voltage Input levels on VCLK pin: High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs Low-level output voltage Low-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current VIH VIL VHYS VOL1 VOL2 ILI ILO CIN, COUT ICC Write ICC Read ICCS 2.0 -- .05 VCC -- -- -10 -10 -- -- -- -- -- .8 .2 VCC -- .4 .6 10 10 10 3 1 30 100 V V V V V A A pF mA mA A A Note 1: 2: This parameter is periodically sampled and not 100% tested. VLCK must be grounded. DS21095J-page 2 2004 Microchip Technology Inc. 24LC21 TABLE 1-2: AC CHARACTERISTICS Standard Mode Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time Output valid from clock Bus free time Symbol Min FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Vcc= 4.5 - 5.5V Fast Mode Min -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns -- -- -- (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated Start condition (Note 2) -- -- (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3) Byte or Page mode -- -- -- -- -- 25C, VCC = 5.0V, Block mode (Note 4) Units Remarks TOF Output fall time from VIH min. to VIL max. Input filter spike suppresTSP sion (SDA and SCL pins) Write cycle time TWR Transmit-only Mode Parameters Output valid from VCLK TVAA VCLK high time TVHIGH VCLK low time TVLOW Mode transition time TVHZ Transmit-only power-up TVPU time Endurance -- Note 1: 2: 3: 4: -- -- -- -- 4000 4700 -- 0 1M 250 50 10 2000 -- -- 500 -- -- 20 + .1 CB -- -- -- 600 1300 -- 0 1M 250 50 10 1000 -- -- 500 -- -- ns ns ms ns ns ns ns ns cycles Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from Microchip's web site at: www.microchip.com 2004 Microchip Technology Inc. DS21095J-page 3 24LC21 2.0 FUNCTIONAL DESCRIPTION The 24LC21 operates in two modes, the Transmit-only mode and the Bidirectional mode. There is a separate two wire protocol to support each mode, each having a separate clock input and sharing a common data line (SDA). The device enters the Transmit-only mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high-to-low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the Bidirectional mode. The only way to switch the device back to the Transmit-only mode is to remove power from the device. mitted on the SDA pin in 8-bit bytes, each followed by a ninth, null bit (see Figure 2-1). The clock source for the Transmit-only mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted Most Significant bit first. Each byte within the memory array will be output in sequence. When the last byte in the memory array is transmitted, the output will wrap around to the first location and continue. The Bidirectional mode Clock (SCL) pin must be held high for the device to remain in the Transmit-only mode. 2.2 Initialization Procedure 2.1 Transmit-only Mode The device will power-up in the Transmit-only mode. This mode supports a unidirectional two wire protocol for transmission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the Transmit-only mode (see Initialization Procedure, below). In this mode, data is trans- After VCC has stabilized, the device will be in the Transmit-only mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal synchronization. During this period, the SDA pin will be in a high-impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the Most Significant bit of a byte. The device will power-up at an indeterminate byte address. (Figure 2-2). FIGURE 2-1: TRANSMIT-ONLY MODE SCL TVAA TVAA SDA Bit 1 (LSB) Null Bit Bit 1 (MSB) Bit 7 VCLK TVHIGH TVLOW FIGURE 2-2: DEVICE INITIALIZATION VCC SCL TVAA TVAA SDA High-impedance for 9 clock cycles TVPU Bit 8 Bit 7 VCLK 1 2 8 9 10 11 DS21095J-page 4 2004 Microchip Technology Inc. 24LC21 3.0 BIDIRECTIONAL MODE 3.1 The 24LC21 can be switched into the Bidirectional mode (see Figure 3-1) by applying a valid high-to-low transition on the Bidirectional mode clock (SCL). When the device has been switched into the Bidirectional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two wire bidirectional data transmission protocol. In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. The bus must be controlled by a master device that generates the Bidirectional mode clock (SCL), controls access to the bus and generates the Start and Stop conditions, while the 24LC21 acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. Bidirectional Mode Bus Characteristics The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (see Figure 3-2). 3.1.1 BUS NOT BUSY (A) Both data and clock lines remain high. 3.1.2 START DATA TRANSFER (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 3.1.3 STOP DATA TRANSFER (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. FIGURE 3-1: SCL MODE TRANSITION Transmit-only mode Bidirectional mode TVHZ SDA VCLK FIGURE 3-2: SCL (A) (B) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (D) (D) (C) (A) SDA Start Condition Address or Acknowledge Valid Data Allowed to Change Stop Condition 2004 Microchip Technology Inc. DS21095J-page 5 24LC21 3.1.4 DATA VALID (D) 3.1.5 ACKNOWLEDGE The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first in first out fashion. Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24LC21 does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition. FIGURE 3-3: BUS TIMING START/STOP VHYS SCL TSU:STA SDA THD:STA TSU:STO Start Stop FIGURE 3-4: BUS TIMING DATA TF THIGH TLOW TR SCL TSU:STA THD:STA THD:DAT TSP TAA THD:STA TAA TSU:DAT TSU:STO SDA IN TBUF SDA OUT DS21095J-page 6 2004 Microchip Technology Inc. 24LC21 3.1.6 SLAVE ADDRESS 4.0 4.1 WRITE OPERATION Byte Write After generating a Start condition, the bus master transmits the slave address consisting of a 7-bit device code `1010' for the 24LC21, followed by three "don't care" bits. The eighth bit of slave address determines if the master device wants to read or write to the 24LC21 (Figure 3-5). The 24LC21 monitors the bus for its corresponding slave address all the time. It generates an Acknowledge bit if the slave address was true and it is not in a programming mode. Operation Read Write Control Code 1010 1010 Chip Select xxx xxx R/W 1 0 FIGURE 3-5: Start CONTROL BYTE ALLOCATION Read/Write Following the Start signal from the master, the slave address (4 bits), the "don't care" bits (3 bits) and the R/W bit which is a logic low, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LC21. After receiving another Acknowledge signal from the 24LC21 the master device will transmit the data word to be written into the addressed memory location. The 24LC21 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24LC21 will not generate Acknowledge signals (Figure 4-1). It is required that VCLK be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. SLAVE ADDRESS R/W A 4.2 1 0 1 0 x x x Page Write The write control byte, word address and the first data byte are transmitted to the 24LC21 in the same way as in a byte write. But instead of generating a Stop condition the master transmits up to eight data bytes to the 24LC21, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a Stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 4-3). 2004 Microchip Technology Inc. DS21095J-page 7 24LC21 It is required that VCLK be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size') and end at addresses that are integer multiples of [page size - 1]. If a page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. FIGURE 4-1: BUS ACTIVITY MASTER S T A R T S BYTE WRITE Control Byte Word Address Data S T O P P A C K A C K A C K SDA LINE BUS ACTIVITY VCLK FIGURE 4-2: BUS ACTIVITY MASTER S T A R T S BYTE WRITE Control Byte Word Address Data S T O P P A C K A C K A C K SDA LINE BUS ACTIVITY VCLK DS21095J-page 8 2004 Microchip Technology Inc. 24LC21 FIGURE 4-3: S T A R T S A C K A C K A C K A C K A C K PAGE WRITE S T O P P BUS ACTIVITY MASTER Control Byte Word Address Data (n) Data (n + 1) Data (n + 15) SDA LINE BUS ACTIVITY VCLK 2004 Microchip Technology Inc. DS21095J-page 9 24LC21 5.0 ACKNOWLEDGE POLLING 6.0 WRITE PROTECTION Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 5-1 for the flow diagram. When using the 24LC21 in the Bidirectional mode, the VCLK pin operates as the write-protect control pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array. Connecting the VCLK pin to VSS would allow the 24LC21 to operate as a serial ROM, although this configuration would prevent using the device in the Transmit-only mode. FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? Yes Next Operation No DS21095J-page 10 2004 Microchip Technology Inc. 24LC21 7.0 READ OPERATION 7.3 Sequential Read Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to `1'. There are three basic types of read operations: current address read, random read and sequential read. Sequential reads are initiated in the same way as a random read except that after the 24LC21 transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24LC21 to transmit the next sequentially addressed 8-bit word (see Figure 7-3). To provide sequential reads the 24LC21 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. 7.1 Current Address Read The 24LC21 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to `1', the 24LC21 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24LC21 discontinues transmission (Figure 7-1). 7.4 Noise Protection The 24LC21 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 7.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC21 as part of a write operation. After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a `1'. The 24LC21 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24LC21 discontinues transmission (Figure 7-2). FIGURE 7-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T S A C K N O A C K Control Byte S T O P P Data (n) SDA LINE BUS ACTIVITY 2004 Microchip Technology Inc. DS21095J-page 11 24LC21 FIGURE 7-2: RANDOM READ Control Byte Word Address S T A R T S A C K A C K A C K N O A C K Control Byte S T O P P S T BUS ACTIVITY A MASTER R T SDA LINE BUS ACTIVITY S Data (n) FIGURE 7-3: SEQUENTIAL READ S T O P P A C K A C K A C K A C K N O A C K BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY Control Byte Data (n) Data (n + 1) Data (n + 2) Data (n + X) DS21095J-page 12 2004 Microchip Technology Inc. 24LC21 8.0 PIN DESCRIPTIONS PIN FUNCTION TABLE Function Ground Serial Address/Data I/O Serial Clock (Bidirectional mode) Serial Clock (Transmit-only mode) +2.5V to 5.5V Power Supply No Connection 8.2 SCL TABLE 8-1: Name VSS SDA SCL VCLK VCC NC This pin is the clock input for the Bidirectional mode, and is used to synchronize data transfer to and from the device. It is also used as the signaling input to switch the device from the Transmit-only mode to the Bidirectional mode. It must remain high for the chip to continue operation in the Transmit-only mode. 8.3 VCLK 8.1 SDA This pin is used to transfer addresses and data into and out of the device, when the device is in the Bidirectional mode. In the Transmit-only mode, which only allows data to be read from the device, data is also transferred on the SDA pin. This pin is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10K for 100 kHz, 2K for 400 kHz). For normal data transfer in the Bidirectional mode, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. This pin is the clock input for the Transmit-only mode. In the Transmit-only mode, each bit is clocked out on the rising edge of this signal. In the Bidirectional mode, a high logic level is required on this pin to enable write capability. 2004 Microchip Technology Inc. DS21095J-page 13 24LC21 9.0 9.1 PACKAGING INFORMATION Package Marking Information 8-Lead PDIP Example XXXXXXXX XXXXXNNN YYWW 24LC21 017 0410 8-Lead SOIC (.150") XXXXXXXX XXXXYYWW NNN Example 24LC21 /SN0410 017 DS21095J-page 14 2004 Microchip Technology Inc. 24LC21 8-Lead Plastic Dual In-line (P) - 300 mil Body (PDIP) E1 D 2 n 1 E A A2 c L A1 eB B1 p B Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX MIN .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2004 Microchip Technology Inc. DS21095J-page 15 24LC21 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil Body (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21095J-page 16 2004 Microchip Technology Inc. 24LC21 APPENDIX A: Revision J Added note to page 1 header (Not recommended for new designs). Added Section 9.0: Package Marking Information. Added On-line Support page. Updated document format. REVISION HISTORY 2004 Microchip Technology Inc. DS21095J-page 17 24LC21 NOTES: DS21095J-page 18 2004 Microchip Technology Inc. 24LC21 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 042003 Connecting to the Microchip Internet Web Site The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 2004 Microchip Technology Inc. DS21095J-page 15 24LC21 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: 24LC21 Questions: 1. What are the best features of this document? Y N Literature Number: DS21095J FAX: (______) _________ - _________ 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21095J-page 16 2004 Microchip Technology Inc. 24LC21 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Device 24LC21: Dual Mode I2CTM Serial EEPROM 24LC21T: Dual Mode I2CTM Serial EEPROM (Tape and Reel) Temperature Range Blank I = 0C to = -40C to +70C +85C Package P SN = = Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2004 Microchip Technology Inc. DS21095J-page 17 24LC21 NOTES: DS21095J-page 18 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. 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